Integrated circuits (or chips) typically comprise a silicon substrate and semiconductor devices, such as transistors, formed from doped regions within the substrate. Interconnect structures, formed in parallel layers overlying the semiconductor substrate and interconnected by vertical conductive vias, provide electrical connection between semiconductor device regions to form electrical circuits.
During the formation of integrated circuits, it is frequently necessary to remove regions of the top layer or layers of a wafer surface. Etching is one process employed to accomplish this material removal. To designate a region to be etched, a thin photoresist material layer is deposited over a wafer surface and patterned by exposing certain regions of the photoresist layer to a controlled pattern of radiation through a mask layer comprising transparent and opaque regions. The radiation passing through the transparent regions causes a chemical reaction in the exposed regions of the photoresist. Visible light, ultraviolet radiation, electron beam energy, or x-ray energy may be used as the developing radiation depending upon the photoresist material selected. A developer is applied to the photoresist layer to dissolve and remove either the radiation exposed areas or the radiation-shielded areas, depending upon the chemistry of the photoresist material.
In either case, a desired region of the underlying substrate is uncovered for exposure to subsequent etching steps through the opening in the photoresist layer, while the regions that remain covered by the photoresist are shielded from subsequent etching steps. If the radiation-exposed areas become less soluble in the developer solution, the non-exposed areas are removed and the pattern remaining on the substrate is a negative image of the pattern of radiation, therefore referred to as a negative photoresist. If the radiation-exposed area becomes more soluble in the developer solution, the pattern remaining on the substrate is a positive image of the pattern of radiation, therefore referred to as a positive photoresist.
Generally, etching processes fall into two categories, wet etching and dry etching. According to a wet etch chemistry, the structure is immersed in or exposed to a liquid chemical bath containing an etchant solution, for example a buffered HF solution. The region to be removed contacts the etchant through the patterned photoresist. Etchants are further subdivided into two broad categories, referred to as isotropic etchants and anisotropic etchants. For the most part, wet etchants tend to be isotropic and dry etchants tend to be anisotropic. Isotropic etchants, which are available for silicon dioxide, nitrides, aluminum, polysilicon, gold, and silicon, attack the material at substantially the same rate in all directions, removing material vertically through the photolithographic etch mask and horizontally under the etch mask. In some applications, significant undesirable horizontal etching, referred to as undercutting, can occur during the isotropic etch process. Anisotropic etchants attack the material layers at different rates in different directions and thus provide more control over the directional aspects of the material removal process. Dry etching uses a gas as the primary etch agent, etching the wafers without the use of wet chemicals or the requirement for rinsing steps after the etch process has been completed.
In addition to geometric selectivity, etchants are also material selective. That is, a specific etch chemistry etches different materials at different etch rates. For example, hydrofluoric acid (HF) etches silicon dioxide but does not effectively etch silicon.
Like all fabrication process steps employed in the manufacture of integrated circuits, the etching process must be carefully controlled to ensure that the electrical and mechanical properties of the resulting semiconductor devices are within their specified parametric range. One important aspect of the etching process is end-point control, i.e., controlling the etch duration by terminating the etch at the appropriate time. Typically, end point control is achieved by choosing an etch chemistry that selectively attacks and removes one or more material layers, without affecting adjacent layers. Positioning an etch-stop layer below the material layer to be removed drastically slows the etch process when the etchant reaches the etch-stop layer. When material of the etch-stop layer is detected in the etch chamber environment, the etch process is terminated.
An exemplary etch process for a semiconductor wafer is illustrated beginning in FIG. 1, depicting a stack 8 comprising in stacked relation, a substrate 10, an etch-stop layer 12, a material layer 14, and a photoresist layer 16. The photoresist layer 16 is patterned as described above to form an opening 18 therein. The stack 8 is exposed to an etchant to remove a region 19 of the material layer 14.
The etch process for removing the region 19 is terminated when the material of the etch-stop layer 12 is detected in the etch chamber. Etching according to this process is referred to as an end-point mode etch. In one embodiment the etch-stop layer 12 comprises silicon nitride. Detection of the etch-stop material is accomplished by sensing an increase in the concentration of nitrogen (for the silicon-nitride etch-stop layer) present in the etch chamber environment, thus indicating that the etch process has reached the etch-stop layer 12. At this point the etch process is terminated as the region 19 of the material layer 14 has been completely removed, forming a opening 20 in the material layer 14. Ideally, there has been no etching of the substrate 10. See FIG. 2. After the etch process is complete, the photoresist layer 16 is removed and the wafer is ready for the next process step.
The end-point material of the etch-stop layer can be detected in the etch chamber using various techniques known in the art, including: ellipsometry, reflectometry, interferometry, and emissivity measurements. In an embodiment where the etch-stop layer 12 comprises silicon dioxide, removal of the material layer 14 can be detected by an increased intensity of the light emitted by the etch by-product carbon monoxide as the etch reactive gasses interact with the etch-stop layer 12.
If, for example, the material layer 14 comprises silicon nitride and the etch chemistry includes fluorocarbons (e.g., CF4, CHF3 and C2F6), cyanide (CN) is produced as a plasma etch by product. The CN reacts with the plasma gasses to produce a spectral component at about 3700 Angstroms. A decrease in the intensity of this spectral component indicates that the etching of the silicon nitride material layer 14 is substantially complete.
Etch chambers can also be equipped with a timer mechanism for triggering an etch stop. An expected etch duration time limit is determined based on the material layer to be removed and the etch process parameters. From the expected duration, low and high time limits are calculated. If the etch process time reaches the low or the high limit prior to detecting the etch-stop material, the etch process is automatically terminated. Use of the timer ensures real time identification of a malfunctioning etch chamber.
In certain etch processes the etching is not necessarily terminated immediately at the end point. Since the etchant may not be distributed uniformly over the wafer, the etch is extended by an over-etch duration to ensure that all regions are removed as intended. Also, the etchant may remove small regions faster than large regions, also necessitating an over-etch period.
Certain etch processes utilize a hard mask in lieu of the photoresist mask formed in the photoresist layer 16 described above. In an exemplary hard mask process a silicon dioxide or silicon nitride layer (not shown in FIGS. 1 or 2) is formed overlying the etch-stop layer 12, for use as a hard mask through which an underlying layer or layers are etched. According to the hard mask process, the photoresist layer 16 is applied over the silicon dioxide layer and the former is patterned as described above. The pattern is then transferred from the photoresist layer 16 to the hard mask layer by etching the hard mask according to the pattern in the photoresist layer 16. The hard mask etch process stops on the etch-stop layer 12. The photoresist layer 16 is removed and the etching steps to form the opening 20 in the material layer 14 are performed using the patterned hard mask layer. This process advantageously offers better dimensional control of the etched features than the standard photoresist etch process.
Within an integrated circuit substrate it may be necessary to isolate certain doped regions to avoid the effects of parasitic devices that are formed as the device doped regions are formed. In particular, in a CMOS (complimentary metal-oxide semiconductor) device proximate n-channel and p-channel devices formed in oppositely-doped wells, lead to the inadvertent formation of parasitic bipolar structures, such as a p-n-p-n thyristor. Although this thyristor operation is inefficient, under certain bias conditions, the p-n-p portion of the structure can supply base current to the n-p-n portion of the structure causing a large current to flow, leading to latch-up of the CMOS device.
Several techniques have been developed for electrically isolating devices to avoid these parasitic effects. One common isolation technique is a local oxidation of silicon (LOCOS) process. LOCOS isolation involves the formation of recessed silicon dioxide material region in a non-active region (also referred to as a field region) of a semiconductor substrate between the p-channel and n-channel devices. According to the conventional LOCOS process, a thin layer of silicon nitride is deposited over the substrate and patterned according to conventional, masking, patterning and etching steps. The isolating silicon dioxide regions are formed by oxidation of the underling silicon in the substrate regions exposed through openings in the silicon nitride, while no oxidation occurs in the in the masked regions.
When LOCOS isolation is employed in the formation of metal-oxide field effect transistors (MOSFETs) in a CMOS circuit, a step is formed between a gate oxide of each MOSFET and a field oxide that forms the LOCOS region. This step, which is about 1500 Angstroms, is generally considered too large to permit accurate photolithographic patterning of device features during subsequent processing steps, especially for devices having a gate thickness of about 0.25 um and smaller. Thus other process steps may be employed to avoid the effects of this oxide step.
Another disadvantage associated with the LOCOS process is the formation of a bird's beak under the silicon nitride layer. At the edges of the silicon nitride masking layer, the silicon dioxide can extend under and lift an edge of the silicon nitride layer. The shape of the LOCOS silicon dioxide at the silicon nitride edge is a gradually tapering wedge, which resembles and is therefore referred to as a bird's beak. In addition to lifting the silicon nitride mask, the bird's beak can also encroach into active regions of the semiconductor device.
Shallow trench isolation (STI) is another known isolation technique that eliminates both the gate oxide-to-field oxide step and the bird's beak. STI uses dielectric filled trenches in the substrate to separate or isolate the semiconductor devices, including CMOS devices and bipolar transistors. STI is an important technology for device sizes of 0.25 microns and below, providing isolation in a smaller surface area and with a flatter upper surface topology than the LOCOS technique.
FIGS. 3–6 are cross-sectional views illustrating the formation of a shallow trench isolation feature according to the prior art. A semiconductor substrate 30 comprises active devices formed within regions depicted generally by a reference character 32. It is desired to isolate these devices with a shallow trench. A plurality of material layers, disposed on an upper surface 33 of the substrate 30, comprise a stress-reducing silicon dioxide layer 36 (also referred to as a pad oxide), a silicon nitride layer 38, and a photoresist layer 40. The photoresist layer 40 is patterned using a mask as described above, to form an opening 41 therein. Using the photoresist layer 40 as an etch mask, a trench 46 (see FIG. 4) is etched in the silicon nitride layer 38, the silicon dioxide layer 36, and through an upper portion of the substrate 30.
The photoresist layer 40 and the silicon nitride layer 38 are removed, and a trench oxide layer 50 is formed or deposited in the trench 46 and on an upper surface 51 of the silicon dioxide layer 36. See FIG. 5. A chemical mechanical polishing step planarizes the upper surface 51, leaving the trench oxide material 50 within the trench 46 and planar with the upper surface 51, forming a shallow trench isolation structure 52 as illustrated in FIG. 6. When the STI process is employed in the formation of CMOS devices the upper surface 51 is substantially planar with an upper surface of the gate oxide layer (also referred to as the thin oxide region), not shown in FIG. 6. Thus the relatively large step that would be formed according to a LOCOS isolation process is absent.
The shallow trench isolation technique requires less area on the substrate surface, as compared with the LOCOS process. Thus the circuit designer can include more transistors per unit area than in designs using LOCOS isolation. STI also provides superior isolation because the sharp corners at the bottom of the trench 46 create voltage barriers that block leakage currents between adjacent semiconductor devices. LOCOS regions generally present rounded corners. Also, the bird's beak is not formed according to the STI process. STI trenches are typically about 3000 Angstroms deep.
One disadvantage associated with the use of shallow trench isolation is the lack of a suitably accurate mechanism for etch end-point detection, i.e., determining when the etch has formed a trench of the desired depth in the substrate 36. Typically, an etch duration is calculated based on the desired trench depth, the material to be etched, the etch chemistry and other known etch process parameters. During the etch process the etch elapsed time is monitored and the etch terminated when the elapsed time reaches the predetermined etch duration. It is known, however, that use of the elapsed time to control the etch duration may not produce repeatable trench depths due to temporal variations in the etch process parameters.
To form trenches of equal depth from wafer-to-wafer (e.g., using a single wafer etcher) or from batch-to-batch (e.g., using a batch reactor), the etch process parameters that affect the etch rate must be carefully monitored and controlled. Off-line metrology tools are used to periodically measure the depth to determine if the process is producing repeatable trench depths that are within a specified range of the desired depth. After processing each cassette of wafers (typically 25 wafers) or at the beginning of each day, the etch depth is measured using a profilometer on an active device wafer in a test structure. If found to be out of specification, the process variables are examined to determine the cause of the anomaly and the process recipe is modified in response thereto.
Several factors can influence the etch rate and thus the trench depth. For example, for a plasma etch process, the RF power supply may have drifted from its required value, thus affecting the etch rate. The mass flow controller that controls the flow of process gas into the etch chamber may not be properly calibrated. The conditions of the etch chamber (e.g., the time interval since the last chamber clean and the type of material etched during the last etch process) can also influence the etch rate.
These etch rate control techniques provide trench depth information for controlling the fabrication process, but they may not provide the desired repeatability and accuracy for trench depth. Nor do they provide real-time control over the etch rate, as the critical measurements are performed off-line and process modifications are initiated only after confirming an out-of-specification trench condition. This is a time-consuming process, resulting in extended fabrication cycles. There is also the cost of the wafer etch rate monitoring equipment to be considered. Finally, if the chamber etch rate drifts between daily or batch measurements, there is a substantial risk of producing defective wafers.